Satellite-based positioning systems include constellations of earth orbiting satellites that constantly transmit orbit information and ranging signals to receivers. An example of a satellite-based positioning system is the Global Positioning System (GPS), with its constellations of GPS satellites. Orbit information and ranging signals transmitted by the GPS satellites are received by GPS receivers. To determine a position, a GPS receiver acquires and tracks satellite signals from three or more GPS satellites to measure its range to the satellites and to demodulate the transmitted orbit information. The architecture of GPS receivers typically has a baseband circuitry to perform the acquisition and tracking of the satellite signals. A GPS receiver also has a processor running navigation software to calculate the receiver position using the measured range and the demodulated satellite orbit information. With increasing integration of GPS receivers into handheld devices such as cellular phones and with GPS receivers operating in ever more challenging signal environment, there is increasing demand for GPS receivers with higher performance and lower power consumption. Conventionally, GPS receivers aim to reduce dynamic power consumption by reducing frequencies of the clocks to the baseband circuitry and the processor. Since dynamic power of CMOS (complementary metal oxide semiconductor) transistors used in digital integrated circuits is a linear function of the CMOS switching frequency, reducing clock frequency reduces dynamic power by the ratio of the frequency reduction relative to the full speed clock. Alternatively, power saving may be realized by running the clock at full speed and then shutting off the clock. This clock gating technique yields power saving that is approximately linear with respect to the duty cycle of the clock being turned off. While both of these techniques are effective in reducing dynamic power to some extent, they have not been optimized for greater power saving because they only manipulate the clock, which is only one variable, in a multi-variable optimization problem.
Dynamic voltage scaling (DVS) is a technique that reduces power consumption by varying the supply voltage as a function of performance requirements. Since CMOS gate switching delay is inversely related to the supply voltage, a change in the supply voltage may also necessitate a change to the clock frequency. Power consumption of CMOS circuitry is a function of both the supply voltage and the switching frequency. DVS seeks to reduce power consumption by operating both the supply voltage and the clock frequency at the lowest level needed to meet system performance requirements. Thus, by lowering both the supply voltage and the clock, DVS is able to achieve greater power saving than that achieved by reducing the clock frequency alone. While DVS has been implemented in processor design for applications where the processor loading requirement is predictable, it has been difficult to adopt DVS in real time signal processing environments such as those encountered by GPS receivers. Therefore, it is desirable to find ways to implement DVS in the baseband and processor of GPS receivers to realize greater power reduction while also meeting stringent real time signal processing and processor throughput requirements of GPS receivers operating in challenging signal conditions.